Thesis Specification


The thesis is about the implementation of a DDR SDRAM Memory Controller that supports the AMBA AHB interface.


The goals for the project are:


2002-09-06Introduction and reading the JEDEC specificationsDone
2002-09-13Design and implementation the memory controllerDone
2002-09-20Working simulation of the memory controllerDone
2002-10-04Design and implementation of the AHB interfaceDone
2002-10-11Working simulation of the AHB interfaceDone
2002-10-25Setting up and running a simulation with an ARM9 CPUCanceled
2002-11-15Synthesis and backannoted simulation of netlistDone
2002-12-06Place and rout with Apollo and simulation of netlistDone
2002-12-13Evaluations and ImprovmentsDone
2002-01-17Writing the final reportDone
2002-01-24Oral presentationDone

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  1. JEDEC Solid State Technology Association
  2. AMBA On-Chip Bus
  3. Collins, Nikel DDR-SDRAM high-speed, source-synchronous interfaces create deisgn callenges
  4. Elpida How to use DDR SDRAM
  5. Vollrath Characterizing SDRAMS
  6. Konishi, Iwamoto, Sawada, Muria, Araki, Kumanoya Dual Clock Scheme for over 200 MHz Synchronous DRAM System
  7. Samsung Electronics Key points for controller design
  8. Lines, Abou-Seido, Mar, Achyuthan, Miyamoto, Murashima, Sakuma High Speed Circuit Techniques in a 150 MHz 64M SDRAM
  9. Davis, Jacobe, Mudge The new DRAM Interfaces: SDRAM, RDRAM and Variants