Theses | Publications (BibTeX)| Chip Designs | Supervision | Teaching | CV

Research

Theses

Book Chapters
  1. M. Själander, M. Martonosi, and S. Kaxiras
    "Power-Efficient Computer Architectures: Recent Advances"
    Synthesis Lectures on Computer Architecture
    Morgan & Claypool, Dec. 2014. ISBN: 978-1-62705-645-8 (BibTeX)
  2. B. Goel, S. A. McKee, and M. Själander
    "Techniques to Measurement, Model, and Manage Power"
    Elsevier Advances in Computers, Green and Sustainable Computing: Part I
    vol. 87, Morgan & Claypool, Nov. 2012. (BibTeX)
Peer-Reviewed Journal Publications
  1. T. Carlson, K.-A. Tran, A. Jimborean, K. Koukos, M. Själander, and S. Kaxiras
    "Transcending Hardware Limits with Software Out-of-order Processing"
    IEEE Computer Architecture Letters
    vol. PP, no. 99, pp. 1-4, Mar. 2017. (BibTeX)
  2. A. Bardizbanyan, M. Själander, D. Whalley, and P. Larsson-Edefors
    "Designing a Practical Data Filter Cache to Improve Both Energy Efficiency and Performance"
    ACM Transactions on Architecture and Code Optimization
    vol. 10, no. 4, pp. 54:1--54:25, Dec. 2013. (BibTeX)
  3. P. Gavin, D. Whalley, and M. Själander
    "Reducing Instruction Fetch Energy in Multi-Issue Processors"
    ACM Transactions on Architecture and Code Optimization
    vol. 10, no. 4, pp. 64:1--64:24, Dec. 2013. (BibTeX)
  4. T. Hoang-Thanh, M. Själander, and P. Larsson-Edefors
    "High-Speed, Energy-Efficient Two-Cycle Multiply-Accumulate (MAC) Architecture and Its Application to a Double-Throughput MAC Unit"
    IEEE Transactions on Circuits and Systems, I: Regular papers, Invited for SOCC Special Issue
    vol. 57, no. 12, pp. 3073-3081, Dec. 2010. (BibTeX)
  5. M. Thuresson, M. Själander, M. Björk, L. Svensson, P. Larsson-Edefors, and P. Stenström
    "FlexCore: Utilizing Exposed Datapath Control for Efficient Computing"
    Journal of Signal Processing Systems
    vol. 57, no. 1, pp. 5-19, Oct. 2009. (BibTeX)
  6. M. Själander, and P. Larsson-Edefors
    "Multiplication Acceleration through Twin Precision"
    IEEE Transactions on Very Large Scale Integration (VLSI) Systems
    vol. 17, no. 9, pp. 1233-1246, Sep. 2009. (BibTeX)
  7. M. Islam, M. Själander, and P. Stenström
    "Early Detection and Bypassing of Trivial Operations to Improve Energy Efficiency of Processors"
    Microprocessors and Microsystems: Embedded Hardware Design
    vol. 32, no. 4, pp. 183-196, Nov. 2008. (BibTeX)
Peer-Reviewed Conference Publications
  1. K.-A. Tran, T. Carlson, K. Koukos, M. Själander, V. Spiliopoilos, S. Kaxiras, and A. Jimborean
    "Clairvoyance: Look-Ahead Compile-time Scheduling"
    Proceedings of the IEEE/ACM International Symposium on Code Generation and Optimization (CGO)
    Austin, Texas, USA, pp. 171-184, 4-8 Feb. 2017. (BibTeX)
  2. C. Sanchez, P. Gavin, D. Moreau, M. Själander, D. Whalley, P. Larsson-Edefors, and S. A. McKee
    "Redesigning a Tagless Access Buffer to Require Minimal ISA Changes"
    Proceedings of the International Conference on Compilers, Architectures and Synthesis for Embedded Systems (CASES)
    Pittsburgh, PA, USA, 2-7 Oct. 2016. (BibTeX)
  3. M. Själander, G. Borgström, M. V. Klymenko, F. Remacle, and S. Kaxiras
    "Techniques for Modulating Error Resilience in Emerging Multi-Value Technologies"
    Proceedings of the ACM International Conference on Computing Frontiers (CF)
    Como, Italy, pp. 55-63, 16-18 May 2016. (BibTeX)
  4. D. Moreau, A. Bardizbanyan, M. Själander, David Whalley, and Per Larsson-Edefors
    "Practical Way Halting by Speculatively Accessing Halt Tags"
    Proceedings of the IEEE International Conference on Design, Automation, and Test in Europe (DATE)
    Dressden, Germany, pp. 1375-1380, 14-18 Mar. 2016. (BibTeX)
  5. B. Davis, P. Gavin, R. Baird, M. Själander, I. Finlayson, F. Rasapour, G. Cook, G.-R. Uh, D. Whalley and G. Tyson
    "Scheduling Instruction Effects for a Statically Pipelined Processor"
    Proceedings of the International Conference on Compilers, Architectures, and Synthesis of Embedded Systems (CASES)
    Amsterdam, Netherlands, pp. 167-176, 4-9 Oct. 2015. (BibTeX)
  6. A. Bardizbanyan, M. Själander, David Whalley, and Per Larsson-Edefors
    "Improving Data Access Efficiency by Using Context-Aware Loads and Stores"
    Proceedings of the ACM International Conference on Languages, Compilers, and Tools for Embedded Systems (LCTES)
    Portland, Oregon, USA, 18-19 June 2015. (BibTeX)
  7. R. Baird, P. Gavin, M. Själander, D. Whalley, and G.-R. Uh
    "Optimizing Transfers of Control in the Static Pipeline Architecture"
    Proceedings of the ACM International Conference on Languages, Compilers, and Tools for Embedded Systems (LCTES)
    Portland, Oregon, USA, pp. 1-10, 18-19 June 2015. (BibTeX)
  8. M. Själander, N. S. Nilsson, and S. Kaxiras
    "A Tunable Cache for Approximate Computing"
    Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH)
    Paris, France, pp. 88-89, 8-9 July 2014. (BibTeX)
  9. A. Bardizbanyan, M. Själander, D. Whalley, and P. Larsson-Edefors
    "Reducing Set-Associative L1 Data Cache Energy by Early Load Data Dependence Detection ELD3"
    Proceedings of the IEEE International Conference on Design, Automation, and Test in Europe (DATE)
    DATE Best Interactive Presentation Award, Dresden, Germany, pp. 82-85, 24-28 Mar. 2014. (BibTeX)
  10. A. Bardizbanyan, M. Själander, D. Whalley, and P. Larsson-Edefors
    "Speculative Tag Access for Reduced Energy Dissipation in Set-Associative L1 Data Caches"
    Proceedings of the IEEE International Conference on Computer Design (ICCD)
    Asheville, North Carolina, USA, pp. 302-308, 6-9 Oct. 2013. (BibTeX)
  11. M. Själander and P. Larsson-Edefors
    "FlexCore: Implementing an Exposed Datapath Processor"
    Proceedings of the IEEE International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS)
    Samos, Greece, pp. 306-313, 15-18 July 2013. (BibTeX)
  12. I. Finlayson, B. Davis, P. Gavin, G.-R. Uh, D. Whalley, M. Själander, and G. Tyson
    "Improving Processor Efficiency by Statically Pipelining Instructions"
    Proceedings of the ACM International Conference on Languages, Compilers, and Tools for Embedded Systems (LCTES)
    Seattle, Washington, USA, pp. 33-43, 20-21 June 2013. (BibTeX)
  13. A. Bardizbanyan, P. Gavin, D. Whalley, M. Själander, P. Larsson-Edefors, S. McKee, and P. Stenström
    "Improving Data Access Efficiency by Using a Tagless Access Buffer (TAB)"
    Proceedings of the IEEE/ACM International Symposium on Code Generation and Optimization (CGO)
    Shenzhen, China, pp. 269-279, 23-27 Feb. 2013. (BibTeX)
  14. V. Saljooghi, A. Bardizbanyan, M. Själander, and P. Larsson-Edefors
    "Configurable RTL Model for Level-1 Caches "
    Proceedings of the IEEE Norchip Conference (NORCHIP)
    Copenhagen, Denmark, pp. 1-4, 12-13 Nov. 2012. (BibTeX)
  15. M. W. Azhar, M. Själander, H. Ali, A. Vijayashekar, T. Hoang-Thanh, K. K. Ansari and P. Larsson-Edefors
    "Viterbi Accelerator for Embedded Processor Datapath"
    Proceedings of the IEEE International Conference on Application-Specific Systems, Architectures and Processors (ASAP)
    Delft, The Netherlands, pp. 133-140, 9-11 July 2012. (BibTeX)
  16. M. Själander, S. A. McKee, P. Brauer, D. Engdal, and A. Vajda
    "An LTE Uplink Receiver PHY Benchmark and Subframe-Based Power Management"
    Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS)
    One of four nominees for best paper award , New Brunswick, New Jersey, USA, pp. 25-34, 1-3 Apr. 2012. (BibTeX)
  17. S. Wong, A. Brandon, F. Anjam, R. Seedorf, R. Giorgi, Z. Yu, N. Puzovic, S. A. McKee, M. Själander, L. Carro, and G. Keramidas
    "Early Results From ERA Embedded Reconfigurable Architectures"
    Proceedings of IEEE International Conference on Industrial Informatics (INDIN)
    Lisbon, Portugal, pp. 816-822, 26-29 July 2011. (BibTeX)
  18. M. Själander, S. A. McKee, B. Goel, P. Brauer, D. Engdal, and A. Vajda
    "Power-Aware Resource Scheduling in Base Stations"
    Proceedings of IEEE International Symposium on Modeling, Analysis and Simulation of Computer and Telecommunication Systems (MASCOTS)
    Singapore, Singapore, pp. 462-465, 25-27 July 2011. (BibTeX)
  19. K. P. Subramaniyan, E. Ryman, M. Själander, T. Hoang-Thanh, M. Islam, and P. Larsson-Edefors
    "FlexDEF: Development Framework for Processor Architecture Implementation and Evaluation"
    Proceedings of Conference on Ph.D Research in Microelectronics and Electronics (PRIME)
    Trento, Italy, pp. 37-40, 3-7 July 2011. (BibTeX)
  20. T. Hoang-Thanh, U. Jälmbrant, E. Hagopian, K. P. Subramaniyan, M. Själander and P. Larsson-Edefors
    "Design Space Exploration for an Embedded Processor with Flexible Datapath Interconnect"
    Proceedings of IEEE International Conference on Application-Specific Systems, Architectures and Processors (ASAP)
    Rennes, France, pp. 55-62, 7-9 July 2010. (BibTeX)
  21. P. Kimfors, N. Broman, A. Haraldsson, K. P. Subramaniyan, M. Själander, H. Eriksson, and P. Larsson-Edefors
    "Custom Layout Strategy for Rectangle-Shaped Log-Depth Multiplier Reduction Tree"
    Proceedings of IEEE International Conference on Electronics, Circuits and Systems (ICECS)
    Hammamet, Tunisia, pp. 77-80, 13-16 Dec. 2009. (BibTeX)
  22. T. Hoang-Thanh, M. Själander, and P. Larsson-Edefors
    "High-Speed, Energy-Efficient 2-Cycle Multiply-Accumulate Architecture"
    Proceedings of IEEE International SoC Conference (SOCC)
    Belfast, Northern Ireland, UK, pp. 119-122, 9-11 Sep. 2009. (BibTeX)
  23. T. Schilling, M. Själander, P. Larsson-Edefors
    "Scheduling for an Embedded Architecture with a Flexible Datapath"
    Proceedings of IEEE Computer Society Annual Symposium on VLSI (ISVLSI)
    Tampa, Florida, USA, pp. 151-156, 13-15 May 2009. (BibTeX)
  24. M. Thuresson, M. Själander, and P. Stenström
    "A Flexible Code-Compression Scheme Using Partitioned Look-Up Tables"
    Proceedings of International Conference on High-Performance and Embedded Architectures and Compilers (HIPEAC)
    Paphos, Cyprus, pp. 95-109, 25-28 Jan. 2009. (BibTeX)
  25. M. Själander, A. Terechko, M. Duranton
    "A Look-Ahead Task Management Unit for Embedded Multi-Core Architectures"
    Proceedings of Euromicro Conference on Digital System Design: Architectures, Methods, and Tools (DSD)
    Parma, Italy, pp. 149-157, 3-5 Sep. 2008. (BibTeX)
  26. M. Själander, and P. Larsson-Edefors
    "High-Speed and Low-Power Multipliers Using the Baugh-Wooley Algorithm and HPM Reduction Tree"
    Proceedings of IEEE International Conference on Electronics, Circuits and Systems (ICECS)
    St. Julian's, Malta, pp. 33-36, 1-3 Sep. 2008. (BibTeX)
  27. M. Thuresson, M. Själander, M. Björk, L. Svensson, P. Larsson-Edefors, and P. Stenström
    "FlexCore: Utilizing Exposed Datapath Control for Efficient Computing"
    Proceedings of IEEE International Symposium on Systems, Architectures, Modeling and Simulation (SAMOS)
    Samos, Greece, pp. 18-25, 16-19 July 2007. (BibTeX)
  28. M. Själander, P. Larsson-Edefors, and M. Björk
    "A Flexible Datapath Interconnect for Embedded Applications"
    Proceedings of IEEE Computer Society Annual Symposium on VLSI (ISVLSI)
    Porto Alegre, Brazil, pp. 15-20, 9-11 Mar. 2007. (BibTeX)
  29. H. Eriksson, P. Larsson-Edefors, M. Sheeran, M. Själander, D. Johansson, M. Schölin
    "Multiplier Reduction Tree with Logarithmic Logic Depth and Regular Connectivity"
    Proceedings of IEEE International Symposium on Circuits and Systems (ISCAS)
    Island of Kos, Greece, pp. 4-8, 21-24 May 2006. (BibTeX)
  30. M. Själander, M. Drazdziulis, P. Larsson-Edefors, and H. Eriksson
    "A Low-Leakage Twin-Precision Multiplier Using Reconfigurable Power Gating"
    Proceedings of IEEE International Symposium on Circuits and Systems (ISCAS)
    Kobe, Japan, pp. 1654-1657, 23-26 May 2005. (BibTeX)
  31. M. Själander, H. Eriksson, P. Larsson-Edefors
    "An Efficient Twin-Precision Multiplier"
    Proceedings of IEEE International Conference on Computer Design (ICCD)
    San Jose, California, pp. 30-33, 10-13 Oct. 2004. (BibTeX)
Peer-Reviewed Workshop and Poster Publications
  1. T. Voigt, M. Själander, Frederik Hermans, Alexandra Jimborean, Erik Hagersten, Per Gunningberg, and Stefanos Kaxiras
    "Poster: Approximation: A New Paradigm also for Wireless Sensing"
    Proceedings of the International Conference on Embedded Wireless Systems and Networks (EWSN)
    Graz, Austria, 15-17 Feb. 2016. (BibTeX)
  2. M. Själander, G. Borgström, and S. Kaxiras
    "Improving Error-Resilience of Emerging Multi-Value Technologies"
    Workshop On Approximate Computing (WAPCO)
    Prague, Czech Republic, 20 Jan. 2016. (BibTeX)
  3. A. Bardizbanyan, M. Själander, D. Whalley, and P. Larsson-Edefors
    "Towards a Performance- and Energy-Efficient Data Filter Cache"
    Proceedings of ACM Workshop on Optimizations for DSP and Embedded Systems (ODES)
    Shenzhen, China, pp. 21-28, 24 Feb. 2013. (BibTeX)
  4. M. Själander, S. A. McKee, B. Goel, P. Brauer, D. Engdal, and A. Vajda
    "Power-Aware Resource Management for LTE Base Stations"
    First International Software Technology Exchange Workshop (STEW)
    Stockholm, Sweden, 23 Nov. 2011. (BibTeX)
  5. G. Goumas, S. A. McKee, M. Själander, T. R. Gross, S. Karlsson, C. W. Probst, and L. Zhang
    "Adapt or Become Extinct!"
    Proceedings of IEEE International Workshop on Adaptive Self-Tuning Computing Systems for the Exaflop Era (EXADAPT)
    San Jose, California, USA, 5 June 2011. (BibTeX)
  6. A. Bardizbanyan, M. Själander, and P. Larsson-Edefors
    "Reconfigurable Instruction Decoding for a Wide-Control-Word Processor"
    Proceedings of IEEE International Reconfigurable Architectures Workshop (RAW)
    Anchorage, Alaska, USA, pp. 322-325, 16-17 May 2011. (BibTeX)
  7. M. Andersson, L. Svensson, M. Själander, S. A. McKee, E. Catovic and P. Ingelhag
    "Yield Optimization Using Redundant Cores"
    Third Swedish Workshop on Multi-Core Computing (MCC)
    Göteborg, Sweden, Oct. 2010. (BibTeX)
  8. T. Hoang-Thanh, M. Själander, and P. Larsson-Edefors
    "Double Throughput Multiply-Accumulate Unit for FlexCore Processor Enhancements"
    Proceedings of IEEE International Reconfigurable Architectures Workshop (RAW)
    Rome, Italy, pp. 1-7, 25-26 May 2009. (BibTeX)
  9. M. Björk, M. Själander, L. Svensson, M. Thuresson, J. Hughes, K. Jeppson, J. Karlsson, P. Larsson-Edefors, M. Sheeran, and P. Stenström
    "Exposed Datapath for Efficient Computing"
    Proceedings of HiPEAC Workshop on Reconfigurable Computing (HIPEAC)
    Ghent, Belgium, 28-30 Jan. 2007. (BibTeX)
Other Publications
  1. N. Frolov, M. Själander, P. Larsson-Edefors, and Sally A. McKee
    "A SAT-Based Compiler for FlexCore"
    Technical report - Department of Computer Science and Engineering, Chalmers University of Technology and Göteborg University
    ISSN: 1652-926X, No: 11-04, Apr. 2011. (BibTeX)
  2. M. Själander, S. A. McKee, B. Goel, P. Brauer, D. Engdal, and A. Vajda,
    "Resource Management for an LTE Baseband Workload"
    Technical report - Department of Computer Science and Engineering, Chalmers University of Technology and Göteborg University
    ISSN: 1652-926X, No: 11-05, Apr. 2011. (BibTeX)
  3. B. Goel, M. Själander, S. A. McKee, V. Spiliopoulos, G. Keramidas, S. Kaxiras and K. Efstathiou
    "Infrastructures for Measuring Power"
    Technical report - Department of Computer Science and Engineering, Chalmers University of Technology and Göteborg University
    ISSN: 1652-926X, No: 11-06, Apr. 2011. (BibTeX)
  4. E. Ryman, K. P. Subramaniyan, T. Hoang-Thanh, M. Islam, M. Själander, and P. Larsson-Edefors
    "FlexTools: Design Space Exploration Tool Chain from C to Physical Implementation"
    CDNLive! EMEA
    Munich, German, 4-6 May 2010. (BibTeX)
  5. J. Andersson, M. Själander, J. Gaisler, and R. Weigand
    "Next Generation Multi-Purpose Microprocessor"
    Proceedings of Data Systems In Aerospace (DASIA)
    Budapest, Hungary, 1-4 June 2010. (BibTeX)
  6. M. Själander, S. Habinc, and J. Gaisler
    "LEON4 Fourth Generation of the LEON Processor"
    Proceedings of Data Systems in Aerospace (DASIA)
    Istanbul, Turkey, 26-29 May 2009. (BibTeX)
  7. T. Hoang-Thanh, M. Själander, and P. Larsson-Edefors
    "Ultra-Low-Power 2-Cycle Multiply-Accumulate Architecture"
    Swedish System-on-Chip Conference (SSoCC)
    Arild, Sweden, 4-5 May 2009. (BibTeX)
  8. U. Jälmbrant, E. Hagopian, M. Själander, and P. Larsson-Edefors
    "Design-Time Scheduling for Processor Exploration"
    Swedish System-on-Chip Conference (SSoCC)
    Arild, Sweden, 4-5 May 2009. (BibTeX)
  9. T. Hoang-Thanh, M. Själander, and P. Larsson-Edefors
    "Double Throughput MAC for Performance Enhancement of the FlexCore Processor"
    Swedish System-on-Chip Conference (SSoCC)
    Gnesta, Sweden, 5-6 May 2008. (BibTeX)
  10. M. Själander, and P. Larsson-Edefors
    "The Case for HPM-Based Baugh-Wooley Multipliers"
    Technical report - Department of Computer Science and Engineering, Chalmers University of Technology and Göteborg University
    ISSN: 1652-926X, No: 08-8, 2008. (BibTeX)
  11. M. Thuresson, M. Själander, P. Stenström
    "A Flexible Code Compression Scheme Using Partitioned Look-Up Tables"
    Technical report - Department of Computer Science and Engineering, Chalmers University of Technology and Göteborg University
    ISSN: 1652-926X, No: 08-15, 2008. (BibTeX)
  12. M. Björk, M. Själander, L. Svensson, M. Thuresson, J. Hughes, K. Jeppson, J. Karlsson, P. Larsson-Edefors, M. Sheeran, and P. Stenström
    "Exposed Datapath for Efficient Computing"
    Technical report - Department of Computer Science and Engineering, Chalmers University of Technology and Göteborg University
    ISSN: 1652-926X, No: 06-21, 2006. (BibTeX)
  13. M. Brinck, K. Eklund, M. Själander, and P. Larsson-Edefors
    "An Efficient FFT Engine Based on Twin-Precision Computation"
    Swedish System-on-Chip Conference (SSoCC)
    Kålmorden, Sweden, 4-5 May 2006. (BibTeX)
  14. M. Själander and P. Larsson-Edefors
    "A Power-Efficient and Versatile Modified-Booth Multiplier"
    Swedish System-on-Chip Conference (SSoCC)
    Tammsvik, Sweden, 18-19 Apr. 2005. (BibTeX)

Patents

Chip Designs

Thesis Supervision
  1. Henrik Grandin
    "Impact of Approximate Data in Arithmetic Operations"
    Uppsala University, Present
  2. Gustaf Borgström
    "Approximative computing for emerging technologies"
    Uppsala University, Present
  3. Vahid Saljooghi
    "Cache Integration and Improvements"
    Chalmers University of Technology, May 2012
  4. Kashan Khurshid Ansari
    "Microcode Optimization in FlexCore Compiler"
    Chalmers University of Technology, March 2012
  5. Hao Li
    "A Cilk implementation of LTE Base-Station Uplink on TILEPro64"
    Chalmers University of Technology, March 2012
  6. Nick Frolov
    "Bau: A Declarative Scheduling Library"
    Chalmers University of Technology, September 2011
  7. Recep Gökhan Aslan and Cemil Caglar Boke
    "DAT095 Project Renewal - Implementation of MP3 Player on FPGA"
    Chalmers University of Technology, August 2011
  8. Johan Ryhd
    "Embedded Camera Remote Control"
    Chalmers University of Technology, August 2011
  9. Ulf Jälmbrant and Erik der Hagopian
    "Improved configurability with FlexSoC For the purpose of design time scheduling for processor exploration"
    Chalmers University of Technology, June 2009
  10. Syed Minhaj Hassan
    "FlexCore: Instruction Decoder and Cache Subsystem"
    Chalmers University of Technology, December 2008
  11. Thomas Schilling
    "Scheduling Techniques for FlexCore"
    Chalmers University of Technology, June 2008
  12. Abdifatah Farah
    "Efficient Datapath Multipliers"
    Chalmers University of Technology, April 2008
  13. Jonas Karlsson
    "A MIPS and NISC implementation"
    Chalmers University of Technology, February 2008
  14. Erik Ryman
    "FlexCore implementation on FPGA"
    Chalmers University of Technology, December 2007
  15. Martin Brink and Kristian Eklund
    "A Flexible FFT/DCT Engine Using the Twin-Precision Technique"
    Chalmers University of Technology, March 2006
  16. Jan Mårts and Tomas Carlqvist
    "A Hardware Audio Decoder Using Flexible Datapaths"
    Chalmers University of Technology, March 2006

Teaching
Thesis Template

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