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Projects | Publications (BibTeX)| Supervision | Teaching | Google Scholar Profile

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Affiliated Research Groups

• The Computing Research Unit at NTNU
• Computer Architecture Lab (CAL) at NTNU
• Energy Efficient Computing Systems (EECS) at NTNU
• Uppsala Architecture Research Team (UART)

Research Projects

• BISMO: A Scalable Bit-Serial Matrix Multiplication Overlay for Reconfigurable Computing
• JLM: An experimental compiler/optimizer using RVSDG as intermediate representation
• SOCRATES: Self-Organizing Computational substRATES
• SpinENGINE: Harnessing the Emergent Properties of Nanomagnet Ensembles for Massively Parallel Data Analysis
• FlexSoC Research project
• Twin-Precision Multipliers
• Power Management for LTE basestations

Conference Lists

• List of VLSI Related Conferences
  
• List of Computer Architecture Related Conferences
  

Theses

1. M. Själander
   "Efficient and Flexible Embedded Systems and Datapath Components"
   Thesis for the Degree of Doctor of Philosophy, Chalmers University of Technology, June 2008, ISSN 0346-718X Technical Report 40D
2. M. Själander
   "Efficient Reconfigurable Multipliers Based on the Twin-Precision Technique"
   Thesis for the Degree of Licentiate of Engineering, Chalmers University of Technology, March 2006, ISSN 1652-876X Technical Report 12L
3. M. Själander
   "Design and Implementation of a DDR SDRAM Controller for System on Chip"
   Thesis for the Degree of Master of Science, Luleå University of Technology, February 2003, ISSN 1402-1617 NR 2003:038

Books and Chapters

1. M. Själander, M. Martonosi, and S. Kaxiras
   "Power-Efficient Computer Architectures: Recent Advances"
   Synthesis Lectures on Computer Architecture
   Morgan & Claypool, Dec. 2014. ISBN: 978-1-62705-645-8 (BibTeX)
2. B. Goel, S. A. McKee, and M. Själander
   "Techniques to Measurement, Model, and Manage Power"
   Elsevier Advances in Computers, Green and Sustainable Computing: Part I
   vol. 87, Morgan & Claypool, Nov. 2012. ISBN: 978-0-12-396528-8 (BibTeX)

Peer-Reviewed Journal Publications

1. S. Saha, S. Chakraborty, S. Agarwal, M. Själander, and K. D McDonald-Maier
   "PRECIOUS: Approximate Real-Time Computing in MLC-MRAM based Heterogeneous CMPs"
   IEEE Transactions on Computers
   vol. 74, no. 10, pp. 3476-3489, July 2025. (BibTeX)
2. S. Chakraborty, T. Bunnam, J. Arunruerk, S. Agarwal, S. Yu, R. Shafik, M. Själander
   "HotReRAM: A Performance-Power-Thermal Simulation Framework for ReRAM Based Caches"
   IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
   vol. 44, no. 9, pp. 3363-3368, Feb. 2025. (BibTeX)
3. S. Saha, S. Chakraborty, S. Agarwal, M. Själander, and K. D McDonald-Maier
   "ARCTIC: Approximate Real-Time Computing in a Cache-Conscious Multicore Environment"
   IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
   vol. 43, no. 10, pp. 2944-2957, Oct. 2024. (BibTeX)
4. D. Metz, V. Kumar, and M. Själander
   "BISDU: A Bit-Serial Dot-Product Unit for Microcontrollers"
   ACM Transactions on Embedded Computing Systems
   vol. 22, no. 5, pp. 1-22, Sep. 2023. (BibTeX)
5. C. Sakalis, S. Kaxiras, and M. Själander
   "Delay-on-Squash: Stopping Microarchitectural Replay Attacks in Their Tracks"
   ACM Transactions on Architecture and Code Optimization (TACO)
   vol. 20, no. 1, pp. 1-24, Mar. 2023. (BibTeX)
6. S. Saha, S. Chakraborty, S. Agarwal, R. Gangopadhyay, M. Själander, and K. D McDonald-Maier
   "DELICIOUS: Deadline-aware approximate computing in cache-conscious multicore"
   IEEE Transactions on Parallel and Distributed Systems
   vol. 34, no. 2, pp. 718-733, Feb. 2023. (BibTeX)
7. J. H. Jensen, A. Stromberg, O. R. Lykkebø, A. Penty, J. Leliaert, M. Själander, E. Folven, and G. Tufte
   "flatspin: A large-scale artificial spin ice simulator"
   Physical Review B
   vol. 106, no. 6, Aug. 2022. (BibTeX)
8. P. Aimoniotis, C. Sakalis, M. Själander, and S. Kaxiras
   "Reorder Buffer Contention: A Forward Speculative Interference Attack for Speculation Invariant Instructions"
   IEEE Computer Architecture Letters (CAL)
   vol. 20, no. 2, pp. 162-165, 2021. (BibTeX)
9. S. Chakraborty and M. Själander
   "WaFFLe: Gated Cache-Ways with Per-core Fine-grained DVFS for Reduced On-chip Temperature and Leakage Consumption"
   ACM Transactions on Architecture and Code Optimization (TACO)
   vol. 18, no. 4, pp. 1-25, Sep. 2021. (BibTeX)
10. S. Chakraborty, S. Saha, M. Själander, and K. Mcdonald-Maier
    "Prepare: Power-Aware Approximate Real-time TaskScheduling for Energy-Adaptive QoS Maximization"
    ACM Transactions on Embedded Computing Systems (TECS)
    vol. 20, no. 5s, pp. 1-25, Sep. 2021. (BibTeX)
11. C. Sakalis, S. Kaxiras, A. Ros, A. Jimborean, and M. Själander
    "Understanding Selective Delay as a Method for Efficient Secure Speculative Execution"
    IEEE Transactions on Computers (IEEE TC)
    vol. 69, no. 11, pp. 1584-1595, Nov. 2020. (BibTeX)
12. N. Reissmann, J. C. Meyer, H. Bahmann, and M. Själander
    "RVSDG: An Intermediate Representation for Optimizing Compilers"
    ACM Transactions on Embedded Computing Systems (TECS)
    vol. 19, no. 6, Dec. 2020. (BibTeX)
13. C. Sakalis, A. Jimborean, S. Kaxiras, and M. Själander
    "Evaluating the Potential Applications of Quaternary Logic for Approximate Computing"
    ACM Journal on Emerging Technologies in Computing Systems (JETC)
    vol. 16, no. 1, Oct. 2019. (BibTeX)
14. Y. Umuroglu, D. Conficconi, L. Rasnayake, T. B Preusser, and M. Själander
    "Optimizing Bit-Serial Matrix Multiplication for Reconfigurable Computing"
    ACM Transactions on Reconfigurable Technology and Systems (TRETS)
    vol. 12, no. 3, pp. 1-24, Aug. 2019. (BibTeX)
15. K.-A. Tran, T. Carlson, K. Koukos, M. Själander, V. Spiliopoulos, S. Kaxiras, and A. Jimborean
    "Static Instruction Scheduling for High Performance on Limited Hardware"
    IEEE Transactions on Computers (IEEE TC)
    vol. 67, no. 4, pp. 513-527, Nov. 2017. (BibTeX)
16. T. Carlson, K.-A. Tran, A. Jimborean, K. Koukos, M. Själander, and S. Kaxiras
    "Transcending Hardware Limits with Software Out-of-order Processing"
    IEEE Computer Architecture Letters (CAL)
    vol. 16, no. 2, pp. 162-165, Feb. 2017. (BibTeX)
17. A. Bardizbanyan, M. Själander, D. Whalley, and P. Larsson-Edefors
    "Designing a Practical Data Filter Cache to Improve Both Energy Efficiency and Performance"
    ACM Transactions on Architecture and Code Optimization (TACO)
    vol. 10, no. 4, pp. 54:1--54:25, Dec. 2013. (BibTeX)
18. P. Gavin, D. Whalley, and M. Själander
    "Reducing Instruction Fetch Energy in Multi-Issue Processors"
    ACM Transactions on Architecture and Code Optimization (TACO)
    vol. 10, no. 4, pp. 64:1--64:24, Dec. 2013. (BibTeX)
19. T. Hoang-Thanh, M. Själander, and P. Larsson-Edefors
    "High-Speed, Energy-Efficient Two-Cycle Multiply-Accumulate (MAC) Architecture and Its Application to a Double-Throughput MAC Unit"
    IEEE Transactions on Circuits and Systems, I: Regular papers, Invited for SOCC Special Issue (TCAS-I)
    vol. 57, no. 12, pp. 3073-3081, Dec. 2010. (BibTeX)
20. M. Thuresson, M. Själander, M. Björk, L. Svensson, P. Larsson-Edefors, and P. Stenström
    "FlexCore: Utilizing Exposed Datapath Control for Efficient Computing"
    Journal of Signal Processing Systems
    vol. 57, no. 1, pp. 5-19, Oct. 2009. (BibTeX)
21. M. Själander, and P. Larsson-Edefors
    "Multiplication Acceleration through Twin Precision"
    IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)
    vol. 17, no. 9, pp. 1233-1246, Sep. 2009. (BibTeX)
22. M. Islam, M. Själander, and P. Stenström
    "Early Detection and Bypassing of Trivial Operations to Improve Energy Efficiency of Processors"
    Microprocessors and Microsystems: Embedded Hardware Design
    vol. 32, no. 4, pp. 183-196, Nov. 2008. (BibTeX)

Peer-Reviewed Conference Publications

1. H. Rognebakke Krogstie, H. Bahmann M. Själander, and N. Reissmann
   "PIP: Making Andersen's Points-to Analysis Sound and Practical for Incomplete C Programs"
   Proceedings of the IEEE/ACM International Symposium on Code Generation and Optimization (CGO)
   Sydney, Asutralia, Feb. 2026. (BibTeX)
2. A. Bergland Kvalsvik and M. Själander
   "ShadowBinding: Realizing Effective Microarchitectures for In-Core Secure Speculation Schemes"
   Proceedings of the ACM/IEEE International Symposium on Microarchitecture (MICRO)
   Seoul, Korea, Oct. 2025. (BibTeX)
3. D. Metz, N. Reissmann, and M. Själander
   "R-HLS: An IR for Dynamic High-Level Synthesis and Memory Disambiguation based on Regions and State Edges"
   Proceedings of the ACM/IEEE International Conference on Computer-Aided Design (ICCAD)
   New Jersey, USA, 2024. (BibTeX)
4. S. Sheikhpour, D. Metz, E. Jellum, M. Själander, and L. Eeckhout
   "Sustainable High-Performance Instruction Selection for Superscalar Processors"
   Proceedings of the ACM/IEEE International Conference on Computer-Aided Design (ICCAD)
   New Jersey, USA, 2024. (BibTeX)
5. S. Chakraborty, S. Saha, M. Själander, and K. D McDonald-Maier
   "MAFin: Maximizing Accuracy in FinFET based Approximated Real-Time Computing"
   Proceedings of the ACM/IEEE International Design Automation Conference (DAC)
   San Francisco, California USA, July 2024. (BibTeX)
6. S. Agarwal, S. Chakraborty; M. Själander
   "TEEMO: Temperature Aware Energy Efficient Multi-Retention STT-RAM Cache Architecture"
   IEEE International Parallel and Distributed Processing Symposium (IPDPS)
   San Francisco, California USA, pp. 852-864, May 2024. (BibTeX)
7. P. Aimoniotis, A. Kvalsvik, M. Själander, and S. Kaxiras
   "ReCon: Efficient Detection, Management, and Use of Non-Speculative Information Leakage"
   Proceedings of the ACM/IEEE International Symposium on Microarchitecture (MICRO)
   Toronto, Canada, pp. 828-842, Oct. 2023. (BibTeX)
8. S. Agarwal, S. Chakraborty, and M. Själander
   "Architecting Selective Refresh based Multi-Retention Cache for Heterogeneous System (ARMOUR)"
   Proceedings of the ACM/IEEE International Design Automation Conference (DAC)
   San Francisco, California USA, July 2023. (BibTeX)
9. A. Kvalsvik, P. Aimoniotis, S. Kaxiras, and M. Själander
   "Doppelganger Loads: A Safe, Complexity-Effective Optimization for Secure Speculation Schemes"
   Proceedings of the ACM/IEEE International Symposium on Computer Architecture (ISCA)
   Orlando, Florida, USA, June 2023. (BibTeX)
10. P. Aimoniotis, A. Kvalsvik, M. Själander, and S. Kaxiras
    "Data-Out Instruction-In (DOIN!): Leveraging Inclusive Caches to Attack Speculative Delay Schemes"
    Proceedings of the IEEE International Symposium on Secure and Private Execution Environment Design (SEED)
    Virtual, pp. 49-60, Sep. 2022. (BibTeX)
11. S. Chakraborty, V. Soteriou, and M. Själander
    "STIFF: Thermally Safe Temperature Effect Inversion Aware Fin FET Based Multi-core"
    Proceedings of the ACM International Conference on Computing Frontiers
    Turin, Italy, pp. 21-29, May 2022. (BibTeX)
12. C. Sakalis, M. Själander, and S.Kaxiras
    "Seeds of SEED: Preventing Priority Inversion in Instruction Scheduling to Disrupt Speculative Interference"
    Proceedings of the IEEE International Symposium on Secure and Private Execution Environment Design (SEED)
    Virtual, Sep. 2021. (BibTeX)
13. C. Sakalis, Z. Chowdhury, S. Wadle, I. Akturk, A. Ros, M. Själander, S.Kaxiras, and U. Karpuzcu
    "Do Not Predict - Recompute! How Value Recomputation Can Truly Boost the Performance of Invisible Speculation"
    Proceedings of the IEEE International Symposium on Secure and Private Execution Environment Design (SEED)
    Virtual, Sep. 2021. (BibTeX)
14. P. Aimoniotis, C. Sakalis, M. Själander, and S.Kaxiras
    "WIP: "It's a trap!" How Speculation Invariance Can Be Abused with Forward Speculative Interference"
    Proceedings of the IEEE International Symposium on Secure and Private Execution Environment Design (SEED)
    Virtual, Sep. 2021. (BibTeX)
15. K.-A. Tran, C. Sakalis, M. Själander, A. Ros, S.Kaxiras, and A. Jimborean
    "Clearing the Shadows: Recovering Lost Performance for Invisible Speculative Execution through HW/SW Co-Design"
    Proceedings of the ACM International Conference on Parallel Architectures and Compilation Techniques (PACT)
    Virtual, pp. 241-254, Oct. 2020. (BibTeX)
16. R. Nishtala, V. Petrucci, P. M. Carpenter, and M. Själander
    "Twig: Multi-Agent Task Management for Colocated Latency-Critical Cloud Services"
    Proceedings of the ACM International Conference on High-Performance Computer Architecture (HPCA)
    San Diego, California, USA, Feb. 2020. (BibTeX)
17. C. Sakalis, S.Kaxiras, A. Ros, A. Jimborean, and M. Själander
    "Efficient Invisible Speculative Execution through Selective Delay and Value Prediction"
    Proceedings of the ACM/IEEE International Symposium on Computer Architecture (ISCA)
    Phoenix, Arizona, USA, June 2019. (BibTeX)
18. C. Sakalis, M. Alipour, A. Ros, A. Jimborean, S. Kaxiras, and M. Själander
    "Ghost Loads: What is the Cost of Invisible Speculation?"
    Proceedings of the ACM International Conference on Computing Frontiers (CF)
    Alghero, Italy, pp. 153-163, May 2019. (BibTeX)
19. Y. Umuroglu, L. Rasnayake, and M. Själander
    "BISMO: A Scalable Bit-Serial Matrix Multiplication Overlay for Reconfigurable Computing"
    Proceedings of the IEEE International Conference on Field-Programmable Logic and Applications (FPL)
    One out of five nominees for the best paper award, Dublin, Ireland, Aug. 2018. (BibTeX)
20. K.-A. Tran, A. Jimborean, T. Carlson, K. Koukos, M. Själander, and S. Kaxiras
    "SWOOP: Software-Hardware Co-Design for Non-Speculative, Execute-Ahead, In-Order Cores"
    Proceedings of the ACM International Conference on Programming Language Design and Implementation (PLDI)
    HiPEAC 2018 Paper Award , Philadelphia, PA, USA, pp. 328-343, June 2018. (BibTeX)
21. K.-A. Tran, T. Carlson, K. Koukos, M. Själander, V. Spiliopoilos, S. Kaxiras, and A. Jimborean
    "Clairvoyance: Look-Ahead Compile-time Scheduling"
    Proceedings of the IEEE/ACM International Symposium on Code Generation and Optimization (CGO)
    Austin, Texas, USA, pp. 171-184, 4-8 Feb. 2017. (BibTeX)
22. C. Sanchez, P. Gavin, D. Moreau, M. Själander, D. Whalley, P. Larsson-Edefors, and S. A. McKee
    "Redesigning a Tagless Access Buffer to Require Minimal ISA Changes"
    Proceedings of the International Conference on Compilers, Architectures and Synthesis for Embedded Systems (CASES)
    Pittsburgh, PA, USA, 2-7 Oct. 2016. (BibTeX)
23. M. Själander, G. Borgström, M. V. Klymenko, F. Remacle, and S. Kaxiras
    "Techniques for Modulating Error Resilience in Emerging Multi-Value Technologies"
    Proceedings of the ACM International Conference on Computing Frontiers (CF)
    Como, Italy, pp. 55-63, 16-18 May 2016. (BibTeX)
24. D. Moreau, A. Bardizbanyan, M. Själander, D. Whalley, and P. Larsson-Edefors
    "Practical Way Halting by Speculatively Accessing Halt Tags"
    Proceedings of the IEEE International Conference on Design, Automation, and Test in Europe (DATE)
    Dresden, Germany, pp. 1375-1380, 14-18 Mar. 2016. (BibTeX)
25. B. Davis, P. Gavin, R. Baird, M. Själander, I. Finlayson, F. Rasapour, G. Cook, G.-R. Uh, D. Whalley and G. Tyson
    "Scheduling Instruction Effects for a Statically Pipelined Processor"
    Proceedings of the International Conference on Compilers, Architectures, and Synthesis of Embedded Systems (CASES)
    Amsterdam, Netherlands, pp. 167-176, 4-9 Oct. 2015. (BibTeX)
26. A. Bardizbanyan, M. Själander, D. Whalley, and P. Larsson-Edefors
    "Improving Data Access Efficiency by Using Context-Aware Loads and Stores"
    Proceedings of the ACM International Conference on Languages, Compilers, and Tools for Embedded Systems (LCTES)
    Portland, Oregon, USA, 18-19 June 2015. (BibTeX)
27. R. Baird, P. Gavin, M. Själander, D. Whalley, and G.-R. Uh
    "Optimizing Transfers of Control in the Static Pipeline Architecture"
    Proceedings of the ACM International Conference on Languages, Compilers, and Tools for Embedded Systems (LCTES)
    Portland, Oregon, USA, pp. 1-10, 18-19 June 2015. (BibTeX)
28. M. Själander, N. S. Nilsson, and S. Kaxiras
    "A Tunable Cache for Approximate Computing"
    Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH)
    Paris, France, pp. 88-89, 8-9 July 2014. (BibTeX)
29. A. Bardizbanyan, M. Själander, D. Whalley, and P. Larsson-Edefors
    "Reducing Set-Associative L1 Data Cache Energy by Early Load Data Dependence Detection ELD3"
    Proceedings of the IEEE International Conference on Design, Automation, and Test in Europe (DATE)
    Best interactive presentation award, Dresden, Germany, pp. 82-85, 24-28 Mar. 2014. (BibTeX)
30. A. Bardizbanyan, M. Själander, D. Whalley, and P. Larsson-Edefors
    "Speculative Tag Access for Reduced Energy Dissipation in Set-Associative L1 Data Caches"
    Proceedings of the IEEE International Conference on Computer Design (ICCD)
    Asheville, North Carolina, USA, pp. 302-308, 6-9 Oct. 2013. (BibTeX)
31. M. Själander and P. Larsson-Edefors
    "FlexCore: Implementing an Exposed Datapath Processor"
    Proceedings of the IEEE International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS)
    Samos, Greece, pp. 306-313, 15-18 July 2013. (BibTeX)
32. I. Finlayson, B. Davis, P. Gavin, G.-R. Uh, D. Whalley, M. Själander, and G. Tyson
    "Improving Processor Efficiency by Statically Pipelining Instructions"
    Proceedings of the ACM International Conference on Languages, Compilers, and Tools for Embedded Systems (LCTES)
    Seattle, Washington, USA, pp. 33-43, 20-21 June 2013. (BibTeX)
33. A. Bardizbanyan, P. Gavin, D. Whalley, M. Själander, P. Larsson-Edefors, S. McKee, and P. Stenström
    "Improving Data Access Efficiency by Using a Tagless Access Buffer (TAB)"
    Proceedings of the IEEE/ACM International Symposium on Code Generation and Optimization (CGO)
    Shenzhen, China, pp. 269-279, 23-27 Feb. 2013. (BibTeX)
34. V. Saljooghi, A. Bardizbanyan, M. Själander, and P. Larsson-Edefors
    "Configurable RTL Model for Level-1 Caches "
    Proceedings of the IEEE Norchip Conference (NORCHIP)
    Copenhagen, Denmark, pp. 1-4, 12-13 Nov. 2012. (BibTeX)
35. M. W. Azhar, M. Själander, H. Ali, A. Vijayashekar, T. Hoang-Thanh, K. K. Ansari and P. Larsson-Edefors
    "Viterbi Accelerator for Embedded Processor Datapath"
    Proceedings of the IEEE International Conference on Application-Specific Systems, Architectures and Processors (ASAP)
    Delft, The Netherlands, pp. 133-140, 9-11 July 2012. (BibTeX)
36. M. Själander, S. A. McKee, P. Brauer, D. Engdal, and A. Vajda
    "An LTE Uplink Receiver PHY Benchmark and Subframe-Based Power Management"
    Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS)
    One out of four nominees for the best paper award, New Brunswick, New Jersey, USA, pp. 25-34, 1-3 Apr. 2012. (BibTeX)
37. S. Wong, A. Brandon, F. Anjam, R. Seedorf, R. Giorgi, Z. Yu, N. Puzovic, S. A. McKee, M. Själander, L. Carro, and G. Keramidas
    "Early Results From ERA - Embedded Reconfigurable Architectures"
    Proceedings of IEEE International Conference on Industrial Informatics (INDIN)
    Lisbon, Portugal, pp. 816-822, 26-29 July 2011. (BibTeX)
38. M. Själander, S. A. McKee, B. Goel, P. Brauer, D. Engdal, and A. Vajda
    "Power-Aware Resource Scheduling in Base Stations"
    Proceedings of IEEE International Symposium on Modeling, Analysis and Simulation of Computer and Telecommunication Systems (MASCOTS)
    Singapore, Singapore, pp. 462-465, 25-27 July 2011. (BibTeX)
39. K. P. Subramaniyan, E. Ryman, M. Själander, T. Hoang-Thanh, M. Islam, and P. Larsson-Edefors
    "FlexDEF: Development Framework for Processor Architecture Implementation and Evaluation"
    Proceedings of Conference on Ph.D Research in Microelectronics and Electronics (PRIME)
    Trento, Italy, pp. 37-40, 3-7 July 2011. (BibTeX)
40. T. Hoang-Thanh, U. Jälmbrant, E. Hagopian, K. P. Subramaniyan, M. Själander and P. Larsson-Edefors
    "Design Space Exploration for an Embedded Processor with Flexible Datapath Interconnect"
    Proceedings of IEEE International Conference on Application-Specific Systems, Architectures and Processors (ASAP)
    Rennes, France, pp. 55-62, 7-9 July 2010. (BibTeX)
41. P. Kimfors, N. Broman, A. Haraldsson, K. P. Subramaniyan, M. Själander, H. Eriksson, and P. Larsson-Edefors
    "Custom Layout Strategy for Rectangle-Shaped Log-Depth Multiplier Reduction Tree"
    Proceedings of IEEE International Conference on Electronics, Circuits and Systems (ICECS)
    Hammamet, Tunisia, pp. 77-80, 13-16 Dec. 2009. (BibTeX)
42. T. Hoang-Thanh, M. Själander, and P. Larsson-Edefors
    "High-Speed, Energy-Efficient 2-Cycle Multiply-Accumulate Architecture"
    Proceedings of IEEE International SoC Conference (SOCC)
    Belfast, Northern Ireland, UK, pp. 119-122, 9-11 Sep. 2009. (BibTeX)
43. T. Schilling, M. Själander, P. Larsson-Edefors
    "Scheduling for an Embedded Architecture with a Flexible Datapath"
    Proceedings of IEEE Computer Society Annual Symposium on VLSI (ISVLSI)
    Tampa, Florida, USA, pp. 151-156, 13-15 May 2009. (BibTeX)
44. M. Thuresson, M. Själander, and P. Stenström
    "A Flexible Code-Compression Scheme Using Partitioned Look-Up Tables"
    Proceedings of International Conference on High-Performance and Embedded Architectures and Compilers (HIPEAC)
    Paphos, Cyprus, pp. 95-109, 25-28 Jan. 2009. (BibTeX)
45. M. Själander, A. Terechko, M. Duranton
    "A Look-Ahead Task Management Unit for Embedded Multi-Core Architectures"
    Proceedings of Euromicro Conference on Digital System Design: Architectures, Methods, and Tools (DSD)
    Parma, Italy, pp. 149-157, 3-5 Sep. 2008. (BibTeX)
46. M. Själander, and P. Larsson-Edefors
    "High-Speed and Low-Power Multipliers Using the Baugh-Wooley Algorithm and HPM Reduction Tree"
    Proceedings of IEEE International Conference on Electronics, Circuits and Systems (ICECS)
    St. Julian's, Malta, pp. 33-36, 1-3 Sep. 2008. (BibTeX)
47. M. Thuresson, M. Själander, M. Björk, L. Svensson, P. Larsson-Edefors, and P. Stenström
    "FlexCore: Utilizing Exposed Datapath Control for Efficient Computing"
    Proceedings of IEEE International Symposium on Systems, Architectures, Modeling and Simulation (SAMOS)
    Samos, Greece, pp. 18-25, 16-19 July 2007. (BibTeX)
48. M. Själander, P. Larsson-Edefors, and M. Björk
    "A Flexible Datapath Interconnect for Embedded Applications"
    Proceedings of IEEE Computer Society Annual Symposium on VLSI (ISVLSI)
    Porto Alegre, Brazil, pp. 15-20, 9-11 Mar. 2007. (BibTeX)
49. H. Eriksson, P. Larsson-Edefors, M. Sheeran, M. Själander, D. Johansson, M. Schölin
    "Multiplier Reduction Tree with Logarithmic Logic Depth and Regular Connectivity"
    Proceedings of IEEE International Symposium on Circuits and Systems (ISCAS)
    Island of Kos, Greece, pp. 4-8, 21-24 May 2006. (BibTeX)
50. M. Själander, M. Drazdziulis, P. Larsson-Edefors, and H. Eriksson
    "A Low-Leakage Twin-Precision Multiplier Using Reconfigurable Power Gating"
    Proceedings of IEEE International Symposium on Circuits and Systems (ISCAS)
    Kobe, Japan, pp. 1654-1657, 23-26 May 2005. (BibTeX)
51. M. Själander, H. Eriksson, P. Larsson-Edefors
    "An Efficient Twin-Precision Multiplier"
    Proceedings of IEEE International Conference on Computer Design (ICCD)
    San Jose, California, pp. 30-33, 10-13 Oct. 2004. (BibTeX)

Peer-Reviewed Workshop and Poster Publications

1. L. Rasnayake and M. Själander
   "Improving Memory Access Locality for Vectorized Bit-Serial Matrix Multiplication in Reconfigurable Computing"
   Proceedings of the International Conference on Field-Programmable Technology (ICFPT)
   , Dec. 2019. (BibTeX)
2. N. Reissmann, J. C. Meyer, and M. Själander
   "RVSDG: An Intermediate Representation for the Multi-Core Era"
   Proceedings of the Nordic Workshop on Multi-Core Computing (MCC)
   , Nov. 2018. (BibTeX)
3. T. Voigt, M. Själander, F. Hermans, A. Jimborean, E. Hagersten, P. Gunningberg, and S. Kaxiras
   "Poster: Approximation: A New Paradigm also for Wireless Sensing"
   Proceedings of the International Conference on Embedded Wireless Systems and Networks (EWSN)
   Graz, Austria, 15-17 Feb. 2016. (BibTeX)
4. M. Själander, G. Borgström, and S. Kaxiras
   "Improving Error-Resilience of Emerging Multi-Value Technologies"
   Workshop On Approximate Computing (WAPCO)
   Prague, Czech Republic, 20 Jan. 2016. (BibTeX)
5. A. Bardizbanyan, M. Själander, D. Whalley, and P. Larsson-Edefors
   "Towards a Performance- and Energy-Efficient Data Filter Cache"
   Proceedings of ACM Workshop on Optimizations for DSP and Embedded Systems (ODES)
   Shenzhen, China, pp. 21-28, 24 Feb. 2013. (BibTeX)
6. M. Själander, S. A. McKee, B. Goel, P. Brauer, D. Engdal, and A. Vajda
   "Power-Aware Resource Management for LTE Base Stations"
   First International Software Technology Exchange Workshop (STEW)
   Stockholm, Sweden, 23 Nov. 2011. (BibTeX)
7. G. Goumas, S. A. McKee, M. Själander, T. R. Gross, S. Karlsson, C. W. Probst, and L. Zhang
   "Adapt or Become Extinct!"
   Proceedings of IEEE International Workshop on Adaptive Self-Tuning Computing Systems for the Exaflop Era (EXADAPT)
   San Jose, California, USA, 5 June 2011. (BibTeX)
8. A. Bardizbanyan, M. Själander, and P. Larsson-Edefors
   "Reconfigurable Instruction Decoding for a Wide-Control-Word Processor"
   Proceedings of IEEE International Reconfigurable Architectures Workshop (RAW)
   Anchorage, Alaska, USA, pp. 322-325, 16-17 May 2011. (BibTeX)
9. M. Andersson, L. Svensson, M. Själander, S. A. McKee, E. Catovic and P. Ingelhag
   "Yield Optimization Using Redundant Cores"
   Third Swedish Workshop on Multi-Core Computing (MCC)
   Göteborg, Sweden, Oct. 2010. (BibTeX)
10. T. Hoang-Thanh, M. Själander, and P. Larsson-Edefors
    "Double Throughput Multiply-Accumulate Unit for FlexCore Processor Enhancements"
    Proceedings of IEEE International Reconfigurable Architectures Workshop (RAW)
    Rome, Italy, pp. 1-7, 25-26 May 2009. (BibTeX)
11. M. Björk, M. Själander, L. Svensson, M. Thuresson, J. Hughes, K. Jeppson, J. Karlsson, P. Larsson-Edefors, M. Sheeran, and P. Stenström
    "Exposed Datapath for Efficient Computing"
    Proceedings of HiPEAC Workshop on Reconfigurable Computing (WRC)
    Ghent, Belgium, 28-30 Jan. 2007. (BibTeX)

Other Publications

1. 
   "Optimizing Energy Efficiency in Subthreshold RISC-V Cores"
   Technical report - arXiv preprint arXiv:2502.06588
   ISSN: , No: , 2025. (BibTeX)
2. M. Själander, M. Jahre, G. Tufte, and N. Reissmann
   "EPIC: An Energy-Efficient, High-Performance GPGPU Computing Research Infrastructure"
   Technical report - arXiv preprint arXiv:1912.05848
   ISSN: , No: , 12 Dec. 2019. (BibTeX)
3. A. Strømberg, A. G. Penty, J. H. Jensen, O. R. Lykkebø, M. Själander, G. Tufte, and E. Folven
   "Unconventional Computing with Artificial Spin Ice"
   Technical report - Frontiers in Artificial Spin Ice
   ISSN: , No: , 06-08 Feb. 2019. (BibTeX)
4. N. Frolov, M. Själander, P. Larsson-Edefors, and Sally A. McKee
   "A SAT-Based Compiler for FlexCore"
   Technical report - Department of Computer Science and Engineering, Chalmers University of Technology and Göteborg University
   ISSN: 1652-926X, No: 11-04, Apr. 2011. (BibTeX)
5. M. Själander, S. A. McKee, B. Goel, P. Brauer, D. Engdal, and A. Vajda,
   "Resource Management for an LTE Baseband Workload"
   Technical report - Department of Computer Science and Engineering, Chalmers University of Technology and Göteborg University
   ISSN: 1652-926X, No: 11-05, Apr. 2011. (BibTeX)
6. B. Goel, M. Själander, S. A. McKee, V. Spiliopoulos, G. Keramidas, S. Kaxiras and K. Efstathiou
   "Infrastructures for Measuring Power"
   Technical report - Department of Computer Science and Engineering, Chalmers University of Technology and Göteborg University
   ISSN: 1652-926X, No: 11-06, Apr. 2011. (BibTeX)
7. E. Ryman, K. P. Subramaniyan, T. Hoang-Thanh, M. Islam, M. Själander, and P. Larsson-Edefors
   "FlexTools: Design Space Exploration Tool Chain from C to Physical Implementation"
   CDNLive! EMEA
   Munich, German, 4-6 May 2010. (BibTeX)
8. J. Andersson, M. Själander, J. Gaisler, and R. Weigand
   "Next Generation Multi-Purpose Microprocessor"
   Proceedings of Data Systems in Aerospace (DASIA)
   Budapest, Hungary, 1-4 June 2010. (BibTeX)
9. M. Själander, S. Habinc, and J. Gaisler
   "LEON4 Fourth Generation of the LEON Processor"
   Proceedings of Data Systems in Aerospace (DASIA)
   Istanbul, Turkey, 26-29 May 2009. (BibTeX)
10. T. Hoang-Thanh, M. Själander, and P. Larsson-Edefors
    "Ultra-Low-Power 2-Cycle Multiply-Accumulate Architecture"
    Swedish System-on-Chip Conference (SSoCC)
    Arild, Sweden, 4-5 May 2009. (BibTeX)
11. U. Jälmbrant, E. Hagopian, M. Själander, and P. Larsson-Edefors
    "Design-Time Scheduling for Processor Exploration"
    Swedish System-on-Chip Conference (SSoCC)
    Arild, Sweden, 4-5 May 2009. (BibTeX)
12. T. Hoang-Thanh, M. Själander, and P. Larsson-Edefors
    "Double Throughput MAC for Performance Enhancement of the FlexCore Processor"
    Swedish System-on-Chip Conference (SSoCC)
    Gnesta, Sweden, 5-6 May 2008. (BibTeX)
13. M. Själander, and P. Larsson-Edefors
    "The Case for HPM-Based Baugh-Wooley Multipliers"
    Technical report - Department of Computer Science and Engineering, Chalmers University of Technology and Göteborg University
    ISSN: 1652-926X, No: 08-8, 2008. (BibTeX)
14. M. Thuresson, M. Själander, P. Stenström
    "A Flexible Code Compression Scheme Using Partitioned Look-Up Tables"
    Technical report - Department of Computer Science and Engineering, Chalmers University of Technology and Göteborg University
    ISSN: 1652-926X, No: 08-15, 2008. (BibTeX)
15. M. Björk, M. Själander, L. Svensson, M. Thuresson, J. Hughes, K. Jeppson, J. Karlsson, P. Larsson-Edefors, M. Sheeran, and P. Stenström
    "Exposed Datapath for Efficient Computing"
    Technical report - Department of Computer Science and Engineering, Chalmers University of Technology and Göteborg University
    ISSN: 1652-926X, No: 06-21, 2006. (BibTeX)
16. M. Brinck, K. Eklund, M. Själander, and P. Larsson-Edefors
    "An Efficient FFT Engine Based on Twin-Precision Computation"
    Swedish System-on-Chip Conference (SSoCC)
    Kålmorden, Sweden, 4-5 May 2006. (BibTeX)
17. M. Själander and P. Larsson-Edefors
    "A Power-Efficient and Versatile Modified-Booth Multiplier"
    Swedish System-on-Chip Conference (SSoCC)
    Tammsvik, Sweden, 18-19 Apr. 2005. (BibTeX)

Patents

• “Modulated Approximation in Logic Circuits”, G.-Z. M. Fernando, S. Kaxiras, and M. Själander, EP16169818.8, 16 May, 2016.
• “Data Filter Cache Designs for Enhancing Energy Efficiancy and Performance in Computing Systems”, D. Whalley, M. Själander, A. Bardizbanyan, and P. Larsson-Edefors, US 20140372700, 29 Aug. 2014.
• "Systems and Methods for Improving Processor Efficiency Through Caching", D. Whalley, M. Själander, A. Bardizbanyan, P. Larsson-Edefors, and P. Gavin, US 20140143494, 19 Nov. 2012.
• "Look-Ahead Task Management", A. Terechko, G. Al-Kadi, M. Duranton, and M. Själander, PCT/IB2009/051035, 12 Mar. 2008.

Postdocs

1. Shounak Chakraborty, NTNU, 2019-present
2. Rajiv Nishtala, NTNU, 2018-2020

Ph.D. Students

1. David Metz, main supervisor, NTNU, 2020-present
2. Amund Bergland Kvalsvik, main supervisor, NTNU, 2020-present
3. Anders Knap Gaustad, main supervisor, NTNU, 2020-present
4. Lahiru Rasnayake, main supervisor, NTNU, 2017-present
5. Chris Sakalis, main supervisor, Uppsala University, 2017-present
6. Nico Reissmann, mentored, NTNU, 2017-2019
7. Alen Bardizbanyan, co-supervisor with Prof. Per Larsson-Edefors, Chalmers, 2010-2013
8. Peter Gavin, mentored with Prof. David Whalley, Chalmers, 2011-2013
9. Bhavishya Goel, mentored with Docent Sally A. McKee, Chalmers, 2011-2012
10. Dmitry Knyaginin, mentored with Docent Sally A. McKee, Chalmers, 2010-2012
11. Tung Hoang Thanh, mentored with Prof. Per Larsson-Edefors, Chalmers, 2008-2010

M.Sc. Thesis Supervision

1. David Mets and Erling Jellum
   "Evaluating FIFO-based Instruction Scheduling Techniques using FPGAs"
   NTNU, 2020
2. Valentin Plotkin
   "Implementation and Evaluation of Data Filter Cache for a RISC-V processor"
   NTNU, 2020
3. Khakim Akhunov
   "Way-predictive instruction cache access in Rocket Chip processor with RISC-V ISA"
   NTNU, 2020
4. Edgar Mo Vedvik
   "Implementing Data Cache Access Memoization (DCAM) in hardware to measure L1 DC and DTLB energy efficiency"
   NTNU, 2019
5. Ludvig Jordet
   "Creation of a software programmable hardware interface"
   NTNU, 2019
6. Kristoffer Monsen
   "Challenges in constructing a RISC-V computing platform"
   NTNU, 2019
7. Martin Gundersen
   "Analyzing an FPGA Neural Net- work Accelerator Design for Imple- mentation in an ASIC"
   NTNU, 2019
8. Erlend Sveen
   "Strict Memory Protection for Microcontrollers&qout;
   NTNU, 2019
9. Håvard Tollefsen
   "Evaluating performance impact of performing computations on storage nodes"
   NTNU, 2018
10. Salahuddin Asjad
    "Energy Efficient Data Accesses"
    NTNU, 2017
11. Henrik Grandin
    "Impact of Approximate Data in Arithmetic Operations"
    Uppsala University, 2015
12. Gustaf Borgström
    "Approximative computing for emerging technologies"
    Uppsala University, 2015
13. Vahid Saljooghi
    "Cache Integration and Improvements"
    Chalmers University of Technology, May 2012
14. Kashan Khurshid Ansari
    "Microcode Optimization in FlexCore Compiler"
    Chalmers University of Technology, March 2012
15. Hao Li
    "A Cilk implementation of LTE Base-Station Uplink on TILEPro64"
    Chalmers University of Technology, March 2012
16. Nick Frolov
    "Bau: A Declarative Scheduling Library"
    Chalmers University of Technology, September 2011
17. Recep Gökhan Aslan and Cemil Caglar Boke
    "DAT095 Project Renewal - Implementation of MP3 Player on FPGA"
    Chalmers University of Technology, August 2011
18. Johan Ryhd
    "Embedded Camera Remote Control"
    Chalmers University of Technology, August 2011
19. Ulf Jälmbrant and Erik der Hagopian
    "Improved configurability with FlexSoC For the purpose of design time scheduling for processor exploration"
    Chalmers University of Technology, June 2009
20. Syed Minhaj Hassan
    "FlexCore: Instruction Decoder and Cache Subsystem"
    Chalmers University of Technology, December 2008
21. Thomas Schilling
    "Scheduling Techniques for FlexCore"
    Chalmers University of Technology, June 2008
22. Abdifatah Farah
    "Efficient Datapath Multipliers"
    Chalmers University of Technology, April 2008
23. Jonas Karlsson
    "A MIPS and NISC implementation"
    Chalmers University of Technology, February 2008
24. Erik Ryman
    "FlexCore implementation on FPGA"
    Chalmers University of Technology, December 2007
25. Martin Brink and Kristian Eklund
    "A Flexible FFT/DCT Engine Using the Twin-Precision Technique"
    Chalmers University of Technology, March 2006
26. Jan Mårts and Tomas Carlqvist
    "A Hardware Audio Decoder Using Flexible Datapaths"
    Chalmers University of Technology, March 2006

Teaching

Course	Period	University
TDT4260 Computer Architecture	Spring 2020	NTNU
TDT4260 Computer Architecture	Spring 2019	NTNU
TDT4260 Computer Architecture	Spring 2018	NTNU
TDT01 Architecture of Computing Systems	Autumn 2017	NTNU
TDT4260 Computer Architecture	Spring 2017	NTNU
TDT4260 Computer Architecture	Spring 2016	NTNU
1DT093 Computer Architecture	LP4 2015	Uppsala University
EEC14 Ph.D. course in "Energy Efficient Computing"	LP4 2014	Uppsala University
Ph.D. course in "Embedded Processor Implementation and Verification"	LP2-LP3 2010/2011	Chalmers
EDA445 VLSI project course	Spring 2007	Chalmers
EDA445 VLSI project course	Spring 2006	Chalmers
EDA445 VLSI project course	Spring 2005	Chalmers
EME010 Digital VLSI Design	LP1 2004	Chalmers
EDA455 System on Chip	LP4 2004	Chalmers
EDA330 Computer System Engineering	LP4 2004	Chalmers
EDA370 Computer System Engineering	Spring 2004	Chalmers
EDA445 VLSI project course	Spring 2004	Chalmers
EDA440 Computer System Engineering	LP3 2004	Chalmers
EME010 Digital VLSI Design	LP1 2003	Chalmers

Thesis Template

Latex Template for Thesis in G5 Format